Units / ECE2072
ECE2072 · Digital systems
2026 Handbook6 credit pointsLevel 2Department of Electrical and Computer Systems Engineering
Last checked: 23 Aug 2026 UTCOverview
This unit introduces you to modern logic design techniques, hardware used and common representations. Topics include two and multi-level combinational logic, decoders, multiplexers, arithmetic circuits, programmable and steering logic, flip-flops, registers, counters, RAM and ROM. Using this hardware the design component will include finite state machine design and applications to computer data path control. This will incorporate simple analogue and digital I/O interfacing. Programmable logic devices will be covered, and the use of a hardware description language for describing, synthesising and testing digital logic. Laboratories cover logic design, implementation, and testing.
Areas of study: E3001 Bachelor of Engineering (Honours) - Specialisation: Electrical and computer systems engineering E3001 Bachelor of Engineering (Honours) - Specialisation: Robotics and mechatronics engineering E6011 Master of Professional Engineering - Specialisation: Electrical engineering S2010 Bachelor of Applied Data Science - Applied studies: Computer systems engineering S3003 Bachelor of Applied Data Science Advanced (Honours) - Applied studies: Computer systems engineering Minor: Semiconductor
Offerings
| Campus | Teaching period | Mode |
|---|---|---|
| Clayton | Second semester | Some activities have a choice of on-campus or online teaching activities (FLEXIBLE) |
| Malaysia | Second semester | Teaching activities are on-campus (ON-CAMPUS) |
Assessment
The Handbook lists an examination for this unit.
| # | Assessment | Type | Weight | Hurdle |
|---|---|---|---|---|
| 1 | Workshop activities | Exercise | 5% | Threshold |
| 2 | Laboratory assessment | Demonstration | 25% | Threshold |
| 3 | Mid-semester test | Quiz / Test | 10% | Threshold |
| 4 | Project | Project | 10% | Threshold |
| 5 | Final assessment | Examination | 50% | Threshold |
Continuous assessment: 50% Final assessment: 50% This unit contains threshold hurdle requirements that you must achieve to be able to pass the unit. You are required to achieve at least 45% in the total continuous assessment component and at least 45% in the final assessment component. The consequence of not achieving a hurdle requirement is a fail grade (NH) and a maximum mark of 45 for the unit.
Assessment details may change. Please refer to the assessment information in Moodle closer to the start of the teaching period.
Requisites
The Handbook lists no prerequisite, corequisite or prohibition for this unit.
Learning outcomes
- Interpret primitive logic circuitry and apply minimisation and realisation techniques to the resultant problems.
- Analyse complex combinational and sequential digital designs using high-level abstractions.
- Propose solutions to real-world specifications by selecting appropriate technologies, such as FPGAs, PLDs and PLCs, and constructing complex digital systems.
- Construct and simulate efficient and effective digital logic designs using integrated development environments and a hardware description language.
- Discuss the fundamental behaviours of digital systems such as time-delay and metastability and interpret their impact on digital systems.
Workload
The minimum total expected workload to achieve the learning outcomes for this unit is 144 hours per semester typically comprising a mixture of 3-6 hours of scheduled learning activities and 6-9 hours of independent study per week. Scheduled activities may include a combination of teacher-directed learning, peer-directed learning and online engagement. Independent study may include associated readings, assessment and preparation for scheduled activities.
| Activity | Duration |
|---|---|
| Laboratories | 22 hours |
| Applied sessions | 24 hours |
| Workshops | 24 hours |
| Assessments | 2 hours |
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