Units / ECE5831
ECE5831 · Microsystem packaging, assembly and testing
2026 Handbook6 credit pointsLevel 5Department of Electrical and Computer Systems Engineering
Last checked: 23 Aug 2026 UTCOverview
In this unit, you’ll cover a broad range of packaging techniques, from traditional methods like leaded and leadless packages, surface mount technology (SMT), and ball grid arrays (BGA), to advanced approaches including 2.5D and 3D packaging, optoelectronics packaging, MEMS and sensor packaging, and memory packaging. You will explore both practical and theoretical aspects of wire bonding, wafer bonding, dicing, and assembly. You will also gain an understanding of key concepts such as reliability analysis, electric shielding, electrostatic discharge, thermal management, and failure analysis under environmental conditions.
Areas of study: E6013 Master of Applied Engineering - Specialisation: Semiconductors and microsystems engineering
Offerings
| Campus | Teaching period | Mode |
|---|---|---|
| Malaysia | Second semester | Teaching activities are on-campus (ON-CAMPUS) |
Assessment
The Handbook lists an examination for this unit.
| # | Assessment | Type | Weight | Hurdle |
|---|---|---|---|---|
| 1 | Assignments | Project | 20% | — |
| 2 | Laboratory and presentation | Demonstration | 20% | — |
| 3 | Test | Examination | 10% | — |
| 4 | Final assessment | Examination | 50% | — |
Continuous assessment: 50% Final assessment: 50%
Assessment details may change. Please refer to the assessment information in Moodle closer to the start of the teaching period.
Requisites
The Handbook lists no prerequisite, corequisite or prohibition for this unit.
Learning outcomes
- Compare different traditional and advanced packaging technologies such as surface mount, ball grid array, 2.5D and 3D packaging employed in the semiconductor industry.
- Demonstrate dicing of wafer and wire bonding die to printed circuit board.
- Interpret challenges and failures in packaging, assembly, reliability of chip and communicate with semiconductor backend experts.
- Analyse reliability of given IC chips and work in a team to prepare a data sheet detailing the results.
Workload
The minimum total expected workload to achieve the learning outcomes for this unit is 144 hours per semester typically comprising a mixture of 3-6 hours of scheduled learning activities and 6-9 hours of independent study per week. Scheduled activities may include a combination of teacher-directed learning, peer-directed learning and online engagement. Independent study may include associated readings, assessment and preparation for scheduled activities.
| Activity | Duration |
|---|---|
| Laboratories | 36 hours |
| Workshops | 24 hours |
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