Units / ECE5063
ECE5063 · Integrated circuit design
2026 Handbook6 credit pointsLevel 5Malaysia School of Engineering
Last checked: 23 Aug 2026 UTCOverview
This unit helps you build a solid understanding of the performance, specification, and fabrication of large-scale digital circuits, including MOS transistor principles, CMOS inverters, building blocks, and interconnects. You’ll explore how to design, simulate, verify, and debug complex digital circuits using a Hardware Description Language (HDL) and current CAD tools with FPGA development boards. You’ll also become familiar with very large-scale integrated (VLSI) circuit design flow methodologies, including layout placement, partitioning, floor planning, and routing.
Areas of study: E6013 Master of Applied Engineering - Specialisation: Semiconductors and microsystems engineering
Offerings
| Campus | Teaching period | Mode |
|---|---|---|
| Malaysia | First semester | Teaching activities are on-campus (ON-CAMPUS) |
Assessment
The Handbook does not list a final examination among the assessment items. That is not a guarantee there is none.
| # | Assessment | Type | Weight | Hurdle |
|---|---|---|---|---|
| 1 | Workshop activities | Exercise | 10% | — |
| 2 | Mid-semester test | Quiz / Test | 15% | — |
| 3 | Laboratory activities | Demonstration | 35% | — |
| 4 | Project | Project | 40% | — |
Continuous assessment: 100% The assessments in this unit are designed to demonstrate the achievement of the advanced learning outcomes and standards expected of Master’s level coursework.
Assessment details may change. Please refer to the assessment information in Moodle closer to the start of the teaching period.
Requisites
prohibitions
- ECE4063 — Large scale digital design
Learning outcomes
- Discuss and evaluate the design process of IC circuits in the semiconductor industry.
- Apply and analyse the principles of CMOS Digital Circuits in case studies and problems.
- Construct a CMOS layout and assess the design in terms of speed, power and area.
- Analyse and evaluate the delay in multiple paths of a VLSI design.
- Design a customised IC circuit based on an industrial design case study and perform full verification on the design for manufacturability.
Workload
The minimum total expected workload to achieve the learning outcomes for this unit is 144 hours per semester typically comprising a mixture of 3-6 hours of scheduled learning activities and 6-9 hours of independent study per week. Scheduled activities may include a combination of teacher-directed learning, peer-directed learning and online engagement. Independent study may include associated readings, assessment and preparation for scheduled activities
| Activity | Duration |
|---|---|
| Laboratories | 24 hours |
| Workshops | 24 hours |
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