ECE4063 · Integrated circuit design

Overview

The unit aims to develop a fundamental understanding of the performance, specification and fabrication of large scale digital circuits. You will become experienced at the design, simulation, verification and debugging of complex large scale digital circuits using a Hardware Description Language (HDL) and current CAD tools with FPGA development boards. Two group design projects will be undertaken: one involving an HDL using FPGA devices and another involving custom VLSI CMOS design and simulation

Areas of study: Minor: Semiconductor

Offerings

Assessment

The Handbook lists an examination for this unit.

Continuous assessment: 60% Final assessment: 40% This unit contains a hurdle requirement that you must achieve to be able to pass the unit. You are required to achieve at least 45% in the total continuous assessment component and at least 45% in the final assessment component. The consequence of not achieving a hurdle requirement is a fail grade (NH) and a maximum mark of 45 for the unit.

Assessment details may change. Please refer to the assessment information in Moodle closer to the start of the teaching period.

Requisites

Learning outcomes

1. Describe the fabrication processes used for producing CMOS VLSI circuits.
2. Apply the principles of CMOS Digital Circuits in case studies and problems.
3. Draw a CMOS layout and assess the design in terms of speed, power and area.
4. Predict and optimise the delay in multiple paths of a VLSI design.
5. Design, implement and debug a complex digital design using HDL as part of a team.

Workload

The minimum total expected workload to achieve the learning outcomes for this unit is 144 hours per semester typically comprising a mixture of 3-6 hours of scheduled learning activities and 6-9 hours of independent study per week. Scheduled activities may include a combination of teacher-directed learning, peer-directed learning and online engagement. Independent study may include associated readings, assessment and preparation for scheduled activities.

Student experience, not official rules. Nothing here changes what the Handbook says.